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(4 votes, average: 5.00 out of 5) Loading ...‘Faulty’ computer chip is 15x more efficient
In terms of speed, energy consumption and size, inexact computer chips like this prototype, are about 15 times more efficient than today’s microchips. (Credit: Avinash Lingamneni/Rice University/CSEM)
RICE (US) — Researchers have created an “inexact” computer chip that’s super efficient, challenging the industry’s 50-year pursuit of accuracy.
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The text of this article by Futurity is licensed under a Creative Commons Attribution-No Derivatives License.
The design improves power and resource efficiency by allowing for occasional errors. Scientists unveiled prototypes this week at the ACMInternational Conference on Computing Frontiers in Cagliari, Italy.
The research, which earned best-paper honors at the conference, was conducted by experts from Rice University, Singapore’s Nanyang Technological University (NTU), Switzerland’s Center for Electronics and Microtechnology (CSEM), and the University of California, Berkeley.
“It is exciting to see this technology in a working chip that we can measure and validate for the first time,” says project leader Krishna Palem, who also serves as director of the Rice-NTU Institute for Sustainable and Applied Infodynamics (ISAID). “Our work since 2003 showed that significant gains were possible, and I am delighted that these working chips have met and even exceeded our expectations.”
This comparison shows frames produced with video-processing software on traditional processing elements (left), inexact processing hardware with a relative error of 0.54 percent (middle) and with a relative error of 7.58 percent (right). The inexact chips are smaller, faster and consume less energy. The chip that produced the frame with the most errors (right) is about 15 times more efficient in terms of speed, space and energy than the chip that produced the pristine image (left). (Credit: Rice University/CSEM/NTU)
ISAID is working in partnership with CSEM to create new technology that will allow next-generation inexact microchips to use a fraction of the electricity of today’s microprocessors.
“The paper received the highest peer-review evaluation of all the Computing Frontiers submissions this year,” says Paolo Faraboschi, the program co-chair of the ACM Computing Frontiers conference and a distinguished technologist at Hewlett Packard Laboratories. “Research on approximate computation matches the forward-looking charter of Computing Frontiers well, and this work opens the door to interesting energy-efficiency opportunities of using inexact hardware together with traditional processing elements.”
The concept is deceptively simple: Slash power use by allowing processing components—like hardware for adding and multiplying numbers—to make a few mistakes. By cleverly managing the probability of errors and limiting which calculations produce errors, the designers have found they can simultaneously cut energy demands and dramatically boost performance.
One example of the inexact design approach is “pruning,” or trimming away some of the rarely used portions of digital circuits on a microchip. Another innovation, “confined voltage scaling,” trades some performance gains by taking advantage of improvements in processing speed to further cut power demands.
In their initial simulated tests in 2011, the researchers showed that pruning some sections of traditionally designed microchips could boost performance in three ways: The pruned chips were twice as fast, used half as much energy and were half the size.
In the new study, the team delved deeper and implemented their ideas in the processing elements on a prototype silicon chip.
“In the latest tests, we showed that pruning could cut energy demands 3.5 timeswith chips that deviated from the correct value by an average of 0.25 percent,” says study co-author Avinash Lingamneni, a Rice graduate student. “When we factored in size and speed gains, these chips were 7.5 times more efficient than regular chips. Chips that got wrong answers with a larger deviation of about 8 percent were up to 15 times more efficient.”
Project co-investigator Christian Enz, who leads the CSEM arm of the collaboration, says: “Particular types of applications can tolerate quite a bit of error. For example, the human eye has a built-in mechanism for error correction. We used inexact adders to process images and found that relative errors up to 0.54 percent were almost indiscernible, and relative errors as high as 7.5 percent still produced discernible images.”
Palem, a computing professor at Rice, who holds a joint appointment at NTU, says likely initial applications for the pruning technology will be in application-specific processors, such as special-purpose “embedded” microchips like those used in hearing aids, cameras, and other electronic devices.
The inexact hardware is also a key component of ISAID’s I-slate educational tablet. The low-cost I-slate is designed for Indian classrooms with no electricity and too few teachers. Officials in India’s Mahabubnagar District announced plans in March to adopt 50,000 I-slates into middle and high school classrooms over the next three years.
The hardware and graphic content for the I-slate are being developed in tandem. Pruned chips are expected to cut power requirements in half and allow the I-slate to run on solar power from small panels similar to those used on handheld calculators. Palem says the first I-slates and prototype hearing aids to contain pruned chips are expected by 2013.
More news from Rice University: http://news.rice.edu/
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9 Comments
Ardianto P. B.
Luiz Roberto Meier
OMG. China will introduce calculators with “almost/close enough” right results. Soon our keyboard will comes only with the symbol ~ , forget the = .
David
Naff article. It talks about ‘pruning’ as being a means to reduce power consumption but yet there is absolutely no actual explanation as to how the power consumption is reduced. Power consumption for MOS integrated circuits is related the frequency of switching of the FET transistors, so if you want to reduce power dissipation you have only three choices: slow the frequency down and or reduce the number of transistors are switching, or reduce the size of the transistors to reduce the gate capacitance.
Avi
@David, That is not entirely true. The power consumption (dynamic) of the CMOS integrated circuits is calculated as
Power consumption (of a gate) = (activity factor) x (load capacitance) x (supply voltage)^2 x (frequency)
This summed over all gates in an integrated circuit gives us the total dynamic power consumption.
As can be seen in the equation, it is essentially based on 4 different attributes : (a) Activity Factor (b) Total Switching capacitance (c) Supply Voltage (d) Frequency of operation. Only (a) & (b) vary from gate to gate in a typical circuit while (c) & (d) are often constant across gates in a circuit (assuming no multiple voltage/frequency islands for now).
The article mentions the following : “One example of the inexact design approach is “pruning,” or trimming away some of the rarely used portions of digital circuits on a microchip. Another innovation, “confined voltage scaling,” trades some performance gains by taking advantage of improvements in processing speed to further cut power demands.”
So, it can be inferred that they are using “pruning” to get its power savings by reducing both (a) and (b) through trimming away the rarely used gates of circuits, i.e. summation of (a) & (b) over lesser number of gates and hence, lesser power consumption. Moreover, they also seem to be using some sort of voltage scaling to quadratically lower power consumption that leads to power savings from the part (c) of the equation. In general, reduction of voltage leads to a linear loss in the speed of the circuit (increases the delay linearly), but as pruning gives some speed gains as well, they seem to be able to trade these speed gains from pruning to be able to realize additional (quadratic) power savings.
Luiz Roberto Meier
@Avi , do you have any suggestion of book(s) about (a) (b) (c) and (d)? I’m trying to study advanced electronics. I do have a degree in advanced mathematics and I work with computers since 1985. I know the basics of digital electronic and I have read the entire (yes) manual of the Intel chips. I started to code in C and Assembly language in 1990. I would like to plot in SAGE the heat and energy in a plane of the above formula. Maybe I’ll do it later. Thank you in advance.
Rob N
Interesting article. They’re looking at analog applications (audio/visual output) where the human brain can cover the small mistakes, but this might have huge implications in artificial intelligence, if we can properly control it. Trying to implement ‘fuzzy logic’ in software has been explored but has limits. This seems to be a totally new way of doing it in hardware.
gwyn jones
Perhaps some unknown nanosoftware is activated in a chip with errors to deal with the errors ??
gj
dhwani
hello…!!!!
dhwani
awesome..breakthrough innovation…!!!
China will lead this