(silicon) Quantum Dots have been used in FLASH Memory for near 5 maybe 7 years, to enhance charge storage density in the Flash memory cells – enabling far higher Flash memory density of late. And photonic applications of QD preceded this by a good number of years. As such since this was supposed to be pathfinding results ( the measurements are good, but not unusual, QD charge properties are well known ) one has to ask what is new here? ( Kelvin Probe
spacial resolution increases in SPM have been around for a while )

Yes the measurement is modestly novel, but the results were and have been well known in REAL devices shipping for large markets of Flash memory devices for quite some time ( see above ).

In Fact IBM Silicon Research did some early work on QD / nanocrystal charge density enhancement in Silicon Flash Memory Devices, by a research team leader who came from Cal Quate’s lab, a graduate of the name of Dr. Catherine Wilder (maiden name – since changed after marrying ).

And that result from Dr. Wilder by now is ancient in the time scale of rapid device technology advances in silicon. Better part of a decade ago.

While the claims are interesting, the key point left out as with many Atom Scale claims ( there are many comparable of technically incomplete process technology ) is that the fundamental charge storage mechanisms have NEVER limited device scaling, ( many folks study charge storage and device physics aplications of QD for quite some time, near since the early to mid 90s, driven by discovery of ability to form QDs in MBE and MOCVD… ( photonics fwiw )

The main limiter for device scaling ALWAYS has been practical means for fabricating ever smaller devices, in development and manufacturing transitions, faster than one’s competitors. ( notably production worthy patterning& layer to layer alignment, as with smaller patterning capability, process technology always rises to the occasion to round out the needed methods )

A few years back a Harvard grad who went on to found a new nanotube memory firm, claimed his new technology for scaling memory would not be limited by lithography ( and practical limits thereof).

In fact they had, in the startup founded, almost to shutter ( certainly deeply retrench initially), because the claims were out and out wrong, and had to pause to figure out how to integrate fluid dispensed nanotubes in a lithography driven processing scheme.

Litho and interconnect and practical means of making electrical contacts to smallest features, have been the dominant drivers / limiters to scaling in process technology of commercial devices from earliest LSI -> VLSI – > ULSI -> practical nanoscale 45-22nm processing of commercial ICs, in high volume manufacturing or even in pilot scale advanced process lines, for real commercial circuits of ANY kind.

Patterning and process integration, not device physics, have been primary limiters to volume commercialization of smaller devices always.

Nice to claim otherwise, but history is rather forceful regarding this sobering matter. The late cofounder of Intel – Dr. Robert Noyce who nearly invented the field of microlithography ( certainly the litho patterned IC ) knew this fact very well.

Moreover, the current advanced topic in transistor technology, a nut not yet cracked open completely ( to commercial standards needed for productization) is the potential application of GRAPHENE as (mostly) a FET ( CMOS or other ) transistor (channel material) technology to leverage the unusually high charge mobilities in a modest cost material ( presently Graphene process costs are dominated by expensive SiC wafers as a means of substrate needed for forming decent graphene over large areas ).

Graphene transistor process technology is in early stages and has some / considerable maturation required before contemplating any serious effort to attempt a 22nm ULSI commercial high integration IC design, or even commercial RF transistors. But given the magnitude of the efforts presently mounted worldwide in Graphene transistor PROCESS R&D, the challenges will likely be overcome, and in time ever faster 22nm and smaller Graphene CMOS / FETS / Bipolar? will poke its head out into the commercial marketplace.

FWIW looking at IEDM conference and other engineering publications will bear this out that Graphene transistor technology is the nexus of advanced nanoscale transistor process R&D. And if I am not mistaken, Dr. Avouris at IBM is one of the world’s leaders in this field, having largely given up hope for the use of nanotubes for practical device R&D in vain hopes for commercialization of nanotube transistors ( vs processabilty of Graphene ). Notable is that Graphene is a planar analog / cousin of carbon nanotubes.

QDs are old, and charge storage properties of QDs are well known and already commercialized in ICs ( Flash memory ) and advanced photonics – lasers and detectors. In fact there is a talented QD expert in the Ottawa region, a near world leader in QDs, who spent time at UCSB under Petroff, in the early days ~’90 of QD experimental science.

Cheers